DSP circuitry may be provided on an integrated circuit (“IC”) in the form of multiple instances (identical or substantially identical repetitions) of a “block” of DSP circuitry. Such a “DSP circuit block” (or “DSP block”) may be capable of several different DSP operations, and the block may be controllable to select which of the possible DSP operations the block performs in any particular application of the IC. For example, the IC may be a programmable logic device (“PLD”), a field-programmable gate array (“FPGA”), or other similar type of device that is manufactured as a relatively general-purpose product that a user can “customize” to perform the functions needed by that user's particular application of the device. Such customization may be by programming function control data into so-called configuration memory cells (configuration random access memory or “CRAM”) on the device. After having been thus programmed or configured, the IC can enter its normal or user mode of operation, in which it performs the functions (e.g., the DSP functions) it has been programmed or configured to perform. Manufacturing such an IC with DSP blocks that can satisfy any of a wide range of possible user needs increases the number of users who can use the IC for their particular applications. This increases the size of the market for the IC, which can benefit the manufacturer; but increased sales volume can also help to lower the unit cost of the IC, which can benefit users of the IC.
One advantageous form of relatively general-purpose DSP block circuitry includes the ability to feed its outputs (i.e., results of DSP operations it has performed) directly or substantially directly into another instance of the same DSP block circuitry on the IC for further processing in that other DSP block (so-called output chaining or cascading). Examples of such advantageous DSP block circuitry are shown in commonly assigned, U.S. patent application Ser. No. 12/380,841, filed Mar. 3, 2009, which is hereby incorporated by reference herein in its entirety.
Among the possible applications of DSP block circuitry of the type mentioned above is in the performance of finite-impulse-response (“FIR”) digital filtering. FIR filtering typically involves passing successive input signal samples through a series of delay circuits, each of which delays each sample applied to it by the time duration of any one sample in the input sample stream. The just-mentioned “time duration” is typically the “period” or time duration of an “operating cycle” of the circuitry, or the period of a clock signal that is used to control the rate of such operating cycles. Each input sample and each sample output by each delay circuit in a given operating cycle of the circuitry is multiplied by a respective filter coefficient value, and all of the resulting multiplication products are added together to produce the output of the FIR filter for that operating cycle.
One possible limitation associated with current FIR filter implementations is that they are typically associated with configurations that are fixed at runtime, and as a result, they are difficult to use in applications that involve dynamic reconfiguration of filter functions or runtime adjustment of filter specifications. With the rising emphasis on rapid and flexible circuit operation and on multi-standard solutions, dynamic filter reconfiguration is an emerging and increasingly important functionality of integrated circuits.